snbk001/Verilog-Design-Examples — GitHub trend

FINDING #1537 · UNIT ID 447973979

snbk001/Verilog-Design-Examples

Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversion, Up down counter, Clock Divider, PIPO, n bit universal shift register, 4 bit LFSR, Single port RAM, Dual port RAM, Synchronous FIFO, Asynchronous FIFO, 8x8 Sequential Multiplier

[ VERILOG ][ GITHUB ↗ ]

SURPRISE SCORE

0.00

Score Breakdown

SURPRISE0.0264

ENGAGEMENT0.73

FRESHNESS1.00

SCORE = SURPRISE × ENGAGEMENT^0.7 × FRESHNESS × VISIBILITY × CONFIDENCE

SURPRISE = WINDOW STARS / DAYS / (AUDIENCE + FLOOR)

4% OF STARS IN ARCHIVE

Growth Telemetry

VELOCITY /D

3.00

ACCEL

+4.00

RETENTION

0.0%

PEAK 2026-09-23 · FORK-RETENTION 0.0% · 9 STARS / WINDOW

Author Audience

AUDIENCE

FOLLOWERS

OWNER ★

278

Engagement Signals

FORKS

ISSUE AUTH

PR AUTH

UNIQUE STARGAZERS 9 / 9 (DIVERSITY 1.00)

Why This Is A Finding

snbk001/Verilog-Design-Examples собрал 9 звёзд за окно, тогда как у автора всего 46 подписчиков — эффективная аудитория ≈ 74. Это даёт surprise-индекс 0.0264 (звёзды относительно охвата автора, а не в абсолюте). Удержание форков 0.0% и 0 внешних контрибьюторов отделяют реальный инструмент от разовой вспышки. Акселерация положительная — рост ещё не выдохся.

Related Findings

RANKS ABOVE 84% OF 9582 FINDINGS

#637fromgof/TridentVision[ VERILOG ]0.0339 #7243The-OpenROAD-Project/OpenROAD[ VERILOG ]0.000255 #9546athralk/TinyGPU[ VERILOG ]<0.000001 #01TheoLeeCJ/SemIf[ PYTHON ]1.84 #02robbietilton/Compositor[ SWIFT ]1.33

METRICS IN CONTEXT

MEDIAN ACROSS ALL 9582 FINDINGS · Δ vs MEDIAN · PERCENTILE = SHARE RANKED BELOW

METRICVALUEMEDIANΔ MEDPERCENTILE

SCORE0.010.00+0.01ABOVE 84%

VELOCITY3.005.67-2.67ABOVE 10%

RETENTION0.0%43.8%-43.8 PPABOVE 0%

FORKS38326-288ABOVE 17%

SURPRISE0.030.00+0.02ABOVE 77%